Happy #FPGAFriday everyone with the #MiSTerFPGA

The FPGA solution that is so nice, I bought it twice.

My town has no water this weekend due to a burst pipe. I could use some #FPGA Friday inspiration right now. Show me your #FPGA projects, however big or small.

To get the ball rolling, here's a little video of a design I've been simulating.☀️

#FPGAFriday fun. See the blinking red LED? (how could you not? 😋 ). Each time it blinks the #gpu is starving: the draw queue is empty as my 6.25MHz CPU is lagging behind. GPU is bored, we need a faster CPU!

💪After One Punch Man, One Pin Video has arrived⚡️😂.
B&W PAL video signal 📺, generated from a single pin of the FPGA (inout - tristate)🤯. Projects with few resources, retro👾...
Follow the thread at twtr.to/H2QTj #FPGAWars #icestudio #FPGAfriday #fpga #FPGAgaming

It seems like forever since I’ve had an #FPGAFriday , but I’ll be dusting off the boards this afternoon to look at a couple of things. Is anyone else playing with FPGAs today?

I learned Verilog this March and finally can make this voxel based ray tracing GPU. It was a fun journey.
#FPGAFriday

Well, it *is* #FPGAFriday 😅

1/N Happy #FPGAFriday ! I just wanted to give a quick description of why this is different than previous designs. None of my previous GPUs were designed to be practically useable. I hardcoded vertices/shaders/texels in a BRAM to test rasterization/texcache/and shaders. They were…

#fpgafriday time for new #yosys #oss -cad-suite-build #iverilog #verilator #openfpgaloader #gtkwave .....github.com/YosysHQ/oss-ca… 💥💥💥💯💯❤️💯💥❤️❤️❤️❤️❤️❤️❤️💯💥💥💯💥💥💥💥❤️❤️💯❤️❤️💯❤️❤️💯❤️😕

#FPGAFriday I am having unreasonable amount of fun with iceBreaker board coding ZX Spectrum ULA like graphics chip over the 640x480 VGA signal!

Added #Speccy loading border emulation just for fun!

github.com/rejunity/fpga-…

Again 😄 #FPGAFriday

#fpgaFriday The KianV series now features an open-source RISC-V architecture with IDs 0x2b. I'm trying to mature the CPU over the next few years. We're still at the beginning, but it's a hobby and it's going on the side, but I'm staying on it... Have a nice weekend.

On FPGAFriday....
I found an error on this bulky expression, (an OR multiplexer)
For some reason, when I activated M_lsbytrcsr[0] or [12] I always got zero instead of a nonzero value. With other bits, I got the correct value. What does two have in common? What did I do wrong?

#fpgafriday #riscv Linux on IceStick !
Olof Kindgren's SERV with bit-serial MMU,
Frequential interleaving for optimal BRAM packing, well beyond the standard 8 kB available on IceStick.
RV32G, multicore version on its way (or framebuffer + HDMI, LOTs of LUTs are still available).

This #FPGAFriday I've been adding branch prediction to the ice-v-swirl, my 4-stages pipelined RISC-V RV32I CPU.
1.2 CPI on the Doomfire demo (1.4 CPI on Dhrystone)
Check it out in #Silice draft branch github.com/sylefeb/Silice…
1/4

Have you discovered any great #FPGA sites this year?

For #FPGA Friday this week, I’m sharing my favourites: projectf.io/recommended-fp…

It's never too late to join the #FPGA Friday party. 100% homegrown graphics hardware and #riscv assembler. #FPGA dev board is Digilent Arty S7-25.

I'm going fixed-point for #FPGAFriday .
I'm experimenting with fixed-point multiplication on 32-bit RISC-V running on #fpga . This is my first attempt, but it seems to work for the few values I've tested. #riscv

Where's our #FPGA Friday goodness, I hear you cry? You'll have to settle for a little bit of my forthcoming #riscv branch post. You want to be able to program all those RISC-V CPUs people keep developing, don't you?

I hope some of our wonderful #FPGA friends share their work too.

Version 0.9 of Icestudio has been Released! 😀🥳
#FPGAFriday #FPGAwars

* Release notes: github.com/FPGAwars/icest…

* Github: github.com/FPGAwars/icest…